A dual mode GHz, UWB and CW, radar transmitter and receiver chip with coding capabilities. The chip is implemented in a Si-BiCMOS process.
Chip is ITAR rated. Under Evaluation, Limited Engagements.
W-band Down Converter
W-band Down Converter
Conversion Gain vs. RF Power
Conversion Gain vs. Swept LO Frequency
Chip is ITAR rated and is available to be evaluated for custom design.
W-band Static Divider
W-band Static Divider
Divider Sensitivity
Implementation of a PLL requires having a millimeter-wave static divider (divide-by 1024) to generate the necessary frequency, to be phase locked to the external crystal oscillator. This divider is also responsible to generate the divide-by-8 frequency which is used as the source for clocking the digital parts (sampling clock and M-sequence speed), as well as the RF-source for the UWB pulse or the PN-CW signal.
Chip is ITAR rated and is available to be evaluated for custom design.
Programmable M-sequencer 10-20GHz
Programmable Sequencer
7th Order
10th Order
Chip is ITAR rated and is available to be evaluated for custom design.
Linear Selector
Linear Selector
Input-Output Linearity
Freqeuncy Response
Chip is ITAR rated and is available to be evaluated for custom design.
Programmable Delay Line
Delay Time vs. Program Code
Measured Results
Chip is ITAR rated and is available to be evaluated for custom design.
Low Phase Noise 5 GHz PLL
A phase noise of better than -110dBc/Hz at 20KHz
Tuning Range
Chip is ITAR rated and is available to be evaluated for custom design.
Wideband, Low Distortion Track and Hold Core for Mixed Signal Applications
Output Compression and Harmonics
Frequency Response
Chip is ITAR rated and is available to be evaluated for purchase.
Testing and measurement of ultra high-speed upper bands of mm-wave signals require availability of a high sampling rate analog-to-digital converter (ADC). This ultra high-speed ADC core can address >25 GHz signal sampling and clocking rate of 60 GHz. The core interfaces to an ultra high-speed de-multiplexer of distributed signal processors.
Please contact our technical literature office to receive the data sheet for this product.
Testing and measurement of ultra high-speed digital I/Os are often met with bottlenecks arising from lack of availability of equipment being capable of handling the upper bands of mm-waves at which the data is fed to digital-to-analog converters. This ultra high-speed multiplexer core can address gearing up of 128 lower speed I/Os at >100 gig-bit-per-second (Gbps) data rate. Unique core has been designed to interface to an ultra high-speed digital-to-analog converter of distributed signal processors with advanced coding systems for wireless applications. The core also addresses the mux function of giga-bit-per-second and terra-bit-per-second optical transceivers, switch and router backplanes, respectively.
Please contact our technical literature office to receive the data sheet for this product.
Testing and measurement of ultra high-speed digital I/Os are often met with bottlenecks arising from lack of availability of equipment being capable of handling the upper bands of mm-waves at which the data is fed from analog-to-digital converters. This ultra high-speed de-multiplexer core can address gearing down to 128 lower speed I/Os at >100 gig-bit-per-second (Gbps) data rate. Unique core has been designed to interface to an ultra high-speed analog-to-digital converter of distributed signal processors with advanced coding systems for wireless applications. The core also addresses the de-mux function of giga-bit-per-second and terra-bit-per-second of optical transceivers, switch and router backplanes, respectively.
Please contact our technical literature office to receive the data sheet for this product.
